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This session will highlight the performance advantages and the compile reductions possible using PlanAhead. It is an easy to use tool that is useful in initial pin assignments, floor-planning the design, launching block based compiles (instead of whole chip compiles), exploring compile options to improve performance, and can take advantage of multiple CPU cores for reduced run times. PlanAhead has been a separate tool in the Xilinx tool chain for the past few years. In the present ISE 10.1 version the pin placement portion was incorporated into the standard design tools. In the coming release, IDS 11.1, which ships the end of March 2009, PlanAhead will be included with all seats. For more information about PlanAhead go to www.xilinx.com/planahead